Scheme. Computer power supply Connecting the power supply at 200w

Here is a complete description of the circuit diagram for one of the 200-watt switching power supplies (PS6220C, made in Taiwan).

The alternating mains voltage is supplied through the PWR SW mains switch through the F101 4A mains fuse, noise suppression filters formed by elements C101, R101, L101, C104, C103, C102 and chokes L102, L103 to:

• output three-pin connector, to which the display power cable can be docked;
• two-pin connector JP1, the counterpart of which is located on the board.

From the JP1 connector, the AC mains voltage is supplied to:

• bridge rectification circuit VR1 through the thermistor THR1;
• the primary winding of the starting transformer T1.

At the output of the rectifier VR1, the smoothing capacitances of the filter C1, C2 are turned on. The THR thermistor limits the initial inrush charging current of these capacitors. The 115V/230V switch SW enables the UPS to be powered both from the 220-240V network and from the 110/127V network.

High-ohmic resistors R1, R2, shunt capacitors C1, C2 are baluns (equalize the voltages on C1 and C2), and also ensure the discharge of these capacitors after the UPS is turned off from the mains. The result of the operation of the input circuits is the appearance on the bus of the rectified voltage of the DC network Uep, equal to +310 V, with some ripples. This UPS uses a start-up circuit with forced (external) excitation, which is implemented on a special starting transformer T1, on the secondary winding of which, after the UPS is connected to the network, an alternating voltage appears with the frequency of the supply network. This voltage is rectified by diodes D25, D26, which form with the secondary winding T1 a full-wave rectification circuit with a midpoint. C30 is the smoothing capacitance of the filter, on which a constant voltage is generated, which is used to power the control chip U4.

The TL494 IC is traditionally used as a control chip in this UPS.

The supply voltage from the capacitor C30 is applied to terminal 12 U4. As a result, the output voltage of the internal reference source Uref = -5 V appears at pin 14 of U4, the internal sawtooth voltage generator of the microcircuit starts, and control voltages appear at pins 8 and 11, which are sequences of rectangular pulses with negative leading edges, shifted relative to each other for half a period. Elements C29, R50, connected to pins 5 and 6 of the U4 chip, determine the frequency of the sawtooth voltage generated by the internal chip generator.

The matching stage in this UPS is made according to a transistorless circuit with separate control. The supply voltage from the capacitor C30 is supplied to the midpoints of the primary windings of the control transformers T2, T3. The output transistors of the IC U4 perform the functions of the matching stage transistors and are connected according to the OE circuit. The emitters of both transistors (pins 9 and 10 of the microcircuit) are connected to the "body". The collector loads of these transistors are the primary half-windings of the control transformers T2, T3, connected to terminals 8, 11 of the U4 microcircuit (open collectors of the output transistors). The other halves of the primary windings T2, T3 with diodes D22, D23 connected to them form the demagnetization circuits of the cores of these transformers.

Transformers T2, T3 control the powerful transistors of the half-bridge inverter.

Switching the output transistors of the microcircuit cause the appearance of pulsed control EMF on the secondary windings of the control transformers T2, T3. Under the influence of these EMF power transistors Q1, Q2 alternately open with adjustable pauses ("dead zones"). Therefore, an alternating current flows through the primary winding of the power pulse transformer T5 in the form of sawtooth current pulses. This is due to the fact that the primary winding T5 is included in the diagonal of the electric bridge, one arm of which is formed by transistors Q1, Q2, and the other by capacitors C1, C2. Therefore, when opening any of the transistors Q1, Q2, the primary winding T5 is connected to one of the capacitors C1 or C2, which causes the current to flow through it during the entire time the transistor is open.

Damper diodes D1, D2 return the energy stored in the leakage inductance of the primary winding T5 during the closed state of transistors Q1, Q2 back to the source (recuperation).

Capacitor C3, connected in series with the primary winding T5, eliminates the DC component of the current through the primary winding T5, thereby eliminating undesirable bias of its core.

Resistors R3, R4 and R5, R6 form the base dividers for power transistors Q1, Q2, respectively, and provide the optimal switching mode in terms of dynamic power losses on these transistors.

The flow of alternating current through the primary winding T5 causes the presence of alternating rectangular pulse EMF on the secondary windings of this transformer.

The power transformer T5 has three secondary windings, each of which has a lead from the midpoint.

Winding IV provides an output voltage of +5 V. Diode assembly SD2 (half-bridge) forms with winding IV a full-wave rectification circuit with a midpoint (the midpoint of winding IV is grounded).

Diodes assembly SD2 are diodes with a Schottky barrier, which achieves the required speed and increases the efficiency of the rectifier.

Winding III together with winding IV provides an output voltage of +12 V together with the diode assembly (half-bridge) SD1. This assembly forms with winding III a full-wave rectification circuit with a midpoint. However, the middle point of winding III is not grounded, but connected to the +5 V output voltage bus. This will make it possible to use Schottky diodes in the +12 V output channel, since the reverse voltage applied to the rectifier diodes during this connection decreases to a level acceptable for Schottky diodes.

Elements L1, C6, C7 form a smoothing filter in the +12 V channel.

Resistors R9, R12 are designed to accelerate the discharge of the output capacitors of the +5 V and +12 V buses after the UPS is turned off from the mains.

Winding II with five taps provides -5 V and -12 V negative output voltages.

Two discrete diodes D3, D4 form a full-wave rectification half-bridge in the -12 V output channel, and diodes D5, D6 - in the -5 V channel.

Elements L3, C14 and L2, C12 form smoothing filters for these channels.

Winding II, as well as winding III, is shunted by a soothing RC circuit R13, C13.

The center point of winding II is grounded.

Stabilization of output voltages is carried out in different ways in different channels.

Negative output voltages -5 V and -12 V are stabilized using linear integrated three-terminal stabilizers U4 (type 7905) and U2 (type 7912).

To do this, the output voltages of the rectifiers from the capacitors C14, C15 are supplied to the inputs of these stabilizers. On the output capacitors C16, C17, stabilized output voltages of -12 V and -5 V are obtained.

Diodes D7, D9 provide discharge of the output capacitors C16, C17 through resistors R14, R15 after the UPS is turned off from the network. Otherwise, these capacitors would be discharged through the stabilizer circuit, which is undesirable.

Through resistors R14, R15, capacitors C14, C15 are also discharged.

Diodes D5, D10 perform a protective function in the event of a breakdown of the rectifier diodes.

If at least one of these diodes (D3, D4, D5 or D6) turns out to be "broken", then in the absence of diodes D5, D10, a positive pulse voltage would be applied to the input of the integral stabilizer U1 (or U2), and through electrolytic capacitors C14 or C15 an alternating current would flow, which would lead to their failure.

The presence of diodes D5, D10 in this case eliminates the possibility of such a situation, because current flows through them.

For example, if the diode D3 is "broken", the positive part of the period when D3 must be closed, the current will close in the circuit: to-and D3 - L3 D7-D5- "case".

Stabilization of the output voltage +5 V is carried out by the PWM method. To do this, a measuring resistive divider R51, R52 is connected to the +5 V output voltage bus. A signal proportional to the output voltage level in the +5 V channel is taken from the resistor R51 and fed to the inverting input of the error amplifier DA3 (pin 1 of the control chip). The direct input of this amplifier (pin 2) is supplied with a reference voltage level, taken from the resistor R48, which is included in the divider VR1, R49, R48, which is connected to the output of the internal reference source of the U4 microcircuit Uref = +5 V. When the voltage level on the bus + 5 V under the influence of various destabilizing factors, there is a change in the magnitude of the mismatch (error) between the reference and controlled voltage levels at the inputs of the error amplifier DA3. As a result, the width (duration) of the control pulses at pins 8 and 11 of the U4 chip changes in such a way as to return the deviated +5 V output voltage to the nominal value (when the voltage on the +5 V bus decreases, the width of the control pulses increases, and when this voltage increases - decreases).

The output voltage +12 V in this UPS is not stabilized.

The output voltage level in this UPS is adjusted only for the +5 V and +12 V channels. This adjustment is carried out by changing the reference voltage level at the direct input of the error amplifier DA3 using the trimmer resistor VR1.

When the position of the VR1 slider is changed during the UPS configuration, the voltage level on the +5 V bus will change within certain limits, and hence on the +12 V bus, because voltage from the +5 V bus is supplied to the middle point of the winding III.

The combined protection of this UPS includes:

• a limiting circuit for controlling the width of the control pulses;
• an incomplete output overvoltage control circuit (only on the +5 V bus).

Let's look at each of these schemes.

The limiting control circuit uses a T4 current transformer as a sensor, the primary winding of which is connected in series with the primary winding of the T5 power pulse transformer.

Resistor R42 is the load of the secondary winding T4, and diodes D20, D21 form a full-wave circuit for rectifying the alternating pulse voltage taken from the load R42.

Resistors R59, R51 form a divider. Part of the voltage is smoothed by capacitor C25. The voltage level on this capacitor proportionally depends on the width of the control pulses at the bases of power transistors Q1, Q2. This level is fed through the resistor R44 to the inverting input of the error amplifier DA4 (pin 15 of the U4 chip). The direct input of this amplifier (pin 16) is grounded. Diodes D20, D21 are connected so that the capacitor C25, when current flows through these diodes, is charged to a negative (relative to the common wire) voltage.

In normal operation, when the width of the control pulses does not go beyond the allowable limits, the potential of pin 15 is positive, due to the connection of this pin through the resistor R45 with the Uref bus. If the control pulse width is increased excessively for any reason, the negative voltage across the capacitor C25 increases, and the potential of output 15 becomes negative. This leads to the output voltage of the error amplifier DA4, which was previously equal to 0 V. A further increase in the width of the control pulses leads to the fact that the switching control of the PWM comparator DA2 is transferred to the amplifier DA4, and the subsequent increase in the width of the control pulses no longer occurs (restricted mode), as the width of these pulses ceases to depend on the level of the feedback signal at the direct input of the error amplifier DA3.

The protection circuit against short circuit in loads can be conditionally divided into protection of channels for generating positive voltages and protection of channels for generating negative voltages, which are implemented in circuitry in approximately the same way.

The sensor of the short circuit protection circuit in the loads of the channels for generating positive voltages (+5 V and +12 V) is a diode-resistive divider D11, R17, connected between the output buses of these channels. The voltage level at the anode of diode D11 is a controlled signal. In normal operation, when the voltages on the output buses of the +5 V and +12 V channels have nominal values, the anode potential of the diode D11 is about +5.8 V, because through the divider-sensor, current flows from the +12 V bus to the +5 V bus along the circuit: +12 V bus - R17-D11 - +5 V bus.

The controlled signal from the anode D11 is fed to the resistive divider R18, R19. Part of this voltage is taken from the resistor R19 and fed to the direct input of the comparator 1 of the U3 chip of the LM339N type. The reference voltage level is supplied to the inverting input of this comparator from the resistor R27 of the divider R26, R27 connected to the output of the reference source Uref=+5 V of the control chip U4. The reference level is chosen such that, during normal operation, the potential of the direct input of comparator 1 would exceed the potential of the inverse input. Then the output transistor of comparator 1 is closed, and the UPS circuit functions normally in PWM mode.

In the event of a short circuit in the load of the +12 V channel, for example, the anode potential of the diode D11 becomes equal to 0 V, so the potential of the inverting input of comparator 1 will become higher than the potential of the direct input, and the output transistor of the comparator will turn on. This will cause the Q4 transistor to close, which is normally open by the base current flowing through the circuit: Upom bus - R39 - R36 b-e Q4 - "body".

Turning on the output transistor of comparator 1 connects resistor R39 to the "body", and therefore transistor Q4 is passively closed by zero bias. Closing the transistor Q4 entails the charging of the capacitor C22, which acts as a protection delay link. The delay is necessary for those reasons that in the process of the UPS entering the mode, the output voltages on the +5 V and +12 V buses do not appear immediately, but as the high-capacity output capacitors charge. The reference voltage from the Uref source, on the contrary, appears almost immediately after the UPS is connected to the network. Therefore, in the starting mode, comparator 1 switches, its output transistor opens, and if there were no delay capacitor C22, this would lead to protection operation immediately when the UPS was turned on. However, C22 is included in the circuit, and the protection operation occurs only after the voltage on it reaches the level determined by the values ​​of the resistors R37, R58 of the divider connected to the Upom bus and which is the base for transistor Q5. When this happens, the transistor Q5 turns on, and the resistor R30 is connected through the small internal resistance of this transistor to the "case". Therefore, a path appears for the base current of transistor Q6 to flow through the circuit: Uref - e-b Q6 - R30 - e-Q5 "case".

Transistor Q6 opens with this current to saturation, as a result of which the voltage Uref = 5 V, which is powered by the emitter of transistor Q6, is applied through its low internal resistance to pin 4 of the control chip U4. This, as shown earlier, leads to the stop of the digital path of the microcircuit, the loss of output control pulses and the termination of switching of power transistors Q1, Q2, i.e. to safety shutdown. A short circuit in the +5 V channel load will cause the anode potential of diode D11 to be only about +0.8 V. Therefore, the output transistor of the comparator (1) will be open and a protective shutdown will occur.

Similarly, short circuit protection is built in the loads of the channels for generating negative voltages (-5 V and -12 V) on the comparator 2 of the U3 microcircuit. Elements D12, R20 form a diode-resistive divider-sensor connected between the output buses of the channels for generating negative voltages. The controlled signal is the potential of the cathode of the diode D12. With a short circuit in the channel load -5 V or -12 V, the potential of the cathode D12 rises (from -5.8 to 0 V with a short circuit in the channel load -12 V and up to -0.8 V with a short circuit in the channel load -5 V) . In any of these cases, the normally closed output transistor of comparator 2 opens, which causes the protection to operate according to the above mechanism. In this case, the reference level from resistor R27 is fed to the direct input of comparator 2, and the potential of the inverting input is determined by the values ​​of resistors R22, R21. These resistors form a bipolar powered divider (resistor R22 is connected to the Uref = +5 V bus, and resistor R21 is connected to the cathode of diode D12, the potential of which in normal UPS operation, as already noted, is -5.8 V). Therefore, the potential of the inverting input of comparator 2 in normal operation is kept lower than the potential of the direct input, and the output transistor of the comparator will be closed.

Protection against output overvoltage on the +5 V bus is implemented on the elements ZD1, D19, R38, C23. The zener diode ZD1 (with a breakdown voltage of 5.1 V) is connected to the +5 V output voltage bus. Therefore, as long as the voltage on this bus does not exceed +5.1 V, the zener diode is closed, and the transistor Q5 is also closed. If the voltage on the +5 V bus increases above +5.1 V, the zener diode “breaks through”, and an unlocking current flows into the base of the transistor Q5, which leads to the opening of the transistor Q6 and the appearance of a voltage Uref = +5 V at pin 4 of the control chip U4, those. to safety shutdown. Resistor R38 is a ballast for the zener diode ZD1. Capacitor C23 prevents the protection from tripping during random short-term voltage surges on the +5 V bus (for example, as a result of voltage establishment after an abrupt decrease in load current). Diode D19 is decoupling.

The PG signal generation circuit in this UPS is dual-functional and is assembled on the comparators (3) and (4) of the U3 microcircuit and the Q3 transistor.

The circuit is based on the principle of controlling the presence of an alternating low-frequency voltage on the secondary winding of the starting transformer T1, which acts on this winding only if there is a supply voltage on the primary winding T1, i.e. while the UPS is connected to the mains.

Almost immediately after the UPS is turned on, the auxiliary voltage Upom appears on the capacitor C30, which powers the control chip U4 and the auxiliary chip U3. In addition, the alternating voltage from the secondary winding of the starting transformer T1 through the diode D13 and the current-limiting resistor R23 charges the capacitor C19. The resistive divider R24, R25 is supplied with voltage from C19. With resistor R25, part of this voltage is applied to the direct input of comparator 3, which leads to the closing of its output transistor. Appearing immediately after this, the output voltage of the internal reference source of the U4 microcircuit Uref = +5 V feeds the divider R26, R27. Therefore, the reference level from the resistor R27 is supplied to the inverting input of the comparator 3. However, this level is chosen to be lower than the level at the direct input, and therefore the output transistor of the comparator 3 remains in the closed state. Therefore, the process of charging the delay capacitance C20 begins along the chain: Upom - R39 - R30 - C20 - "body".

The voltage growing as the capacitor C20 charges is applied to the inverse input 4 of the U3 microcircuit. The direct input of this comparator is supplied with voltage from the resistor R32 of the divider R31, R32 connected to the Upom bus. As long as the voltage on the charging capacitor C20 does not exceed the voltage on the resistor R32, the output transistor of the comparator 4 is closed. Therefore, the opening current flows into the base of the transistor Q3 through the circuit: Upom - R33 - R34 - b-e Q3 - "case".

Transistor Q3 is open to saturation, and the PG signal taken from its collector is passive low and prohibits the processor from starting. During this time, during which the voltage level on the capacitor C20 reaches the level on the resistor R32, the UPS manages to reliably enter the nominal operating mode, i.e. all its output voltages appear in full.

As soon as the voltage at C20 exceeds the voltage taken from R32, comparator 4 will switch and its output transistor will turn on. This will cause transistor Q3 to close, and the PG signal, taken from its collector load R35, becomes active (H-level) and allows the processor to start.

When the UPS is turned off from the mains, the alternating voltage disappears on the secondary winding of the starting transformer T1. Therefore, the voltage across the capacitor C19 decreases rapidly due to the low capacitance of the latter (1 microfarad).

As soon as the voltage drop across resistor R25 becomes less than that across resistor R27, comparator 3 will switch and its output transistor will turn on. This will entail a protective shutdown of the output voltages of the control chip U4, because. open transistor Q4. In addition, through the open output transistor of the comparator 3, the process of accelerated discharging of the capacitor C20 along the circuit will begin: (+) C20 - R61 - D14 - k-e of the output transistor of the comparator 3 - "case". As soon as the voltage level at C20 becomes less than the voltage level at R32, comparator 4 will switch and its output transistor will turn off. This will cause Q3 to turn on and the PG signal to go inactive low before the UPS output bus voltages begin to drop unacceptably. This will initialize the system reset signal of the computer and reset the entire digital part of the computer.

Both comparators 3 and 4 of the PG signal generation circuit are covered by positive feedback with resistors R28 and R60 respectively, which speeds up their switching.

A smooth transition to the mode in this UPS is traditionally provided using the forming chain C24, R41, connected to pin 4 of the U4 control chip. The residual voltage at pin 4, which determines the maximum possible duration of the output pulses, is set by the divider R49, R41.

The fan motor is powered by voltage from the capacitor C14 in the -12 V voltage generation channel through an additional decoupling L-shaped filter R16, C15.